* Double-data-rate architecture: two data transfers per clock cycle
* The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
*.

2G bits DDR3 SDRAM

EDJ2108DEBG

EDJ1108DBSE

EDJ1108DJBG

EDJ1116DBSE

EDJ1116DJBG

EDJ4204EFBG

EDJ4208EFBG

EDJ4208EFBG-L

EDJ4216EFBG

EDJ4216EFBG-L

ED-11

ED-15

ED-205

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